This invention relates generally to a digital logic circuit. More particularly, it related to a logic input buffer and related circuitry.
Digital logic circuits are used for various electronic applications such as microprocessors, controllers, digital signal processors, memory devices, etc. Digital logic circuits can be classified into three popular logic families: (1) transistor-transistor logic (TTL), (2) emitter-coupled logic (ECL), and complementary metal-oxide-semiconductor (CMOS). CMOS logic circuits offer advantages over other logic families because of its low dissipation power, compact design, and noise immunity.
For a digital logic circuit, each input signal is typically provided to an input logic buffer within the logic circuit. A simplified schematic of a generic CMOS inverting input buffer 100 is shown in FIG. 1A. The input buffer 100 has two input transistors, a P-channel transistor 112 and an N-channel transistor 114, coupled in series. The input transistors 112 and 114 are MOS enhancement mode devices. The source of the upper P-channel transistor 112 couples to an upper power supply (VDD) and the source of the lower N-channel transistor 114 couples to a lower power supply (VSS). The gates of both transistors couple together and comprise the input of the buffer 100. The drains of both transistors couple together and comprise the output of the buffer 100.
A set of considerations is taken into account in the design of the input buffer 100. These considerations include: (1) DC specifications, (2) noise margin, (3) noise immunity, (4) cross current, (5) circuit size, (6) switching speed, and so on. Digital logic circuits are characterized, in part, by their DC specifications. The DC specifications include: (1) the logic high input voltage threshold V.sub.IH, (2) the logic low input voltage threshold V.sub.IL, (3) the logic high output voltage V.sub.OH, and (4) the logic low output voltage V.sub.OL. Generally, an input signal having a voltage above V.sub.IH is considered a logic high input and a voltage below V.sub.IL is considered a logic low input. The V.sub.IH and V.sub.IL are the input "trip" points at which the logic circuit changes state. An output signal is above V.sub.OH volts for a logic high output and below V.sub.OL volts for a logic low output.
Usually, by varying the betas of the transistors, the designer can alter the characteristics of the circuit to affect one or more of the above considerations. Generally, the circuit designer selects the betas of the transistors (e.g., the betas of the P-channel transistor 112 and the N-channel transistor 114) and the ratio of the transistor betas, such that the most favorable characteristics are obtained. The betas, in turn, can be controlled by proper sizing of the transistors. Because the degree of control is limited for the number of considerations, a suboptimal circuit design is typically produced.